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112G-ELR PAM4 SerDes PHY - TSMC 5nm
112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channels for HPC SoCs.
The Cadence 112Gbps Multi-Rate Extended Long-Reach (ELR) PHY IP for TSMC 5nm operates at 56-112Gbps using PAM4 modulation or 1-56Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The ELR PHY provides additional performance margin to high-loss and reflective channels by incorporating reflection cancellation and enhanced digital signal processing. The area- and poweroptimized design is ideal for high port-density applications that require ELR performance.
The Cadence 112Gbps Multi-Rate Extended Long-Reach (ELR) PHY IP for TSMC 5nm operates at 56-112Gbps using PAM4 modulation or 1-56Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The ELR PHY provides additional performance margin to high-loss and reflective channels by incorporating reflection cancellation and enhanced digital signal processing. The area- and poweroptimized design is ideal for high port-density applications that require ELR performance.
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Serdes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency