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112G-ELR PAM4 SerDes PHY
112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channels for HPC SoCs.
The Cadence 112Gbps Extended Long-Reach (ELR) SerDes IP for TSMC 7nm/6nm operates at a full-rate of 112Gbps using PAM4 modulation and half-rate of 56Gbps using PAM4 modulation, as well as 56/28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The ELR PHY provides additional performance margin to highloss and reflective channels by incorporating reflection cancellation and enhanced digital signal processing. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links
The Cadence 112Gbps Extended Long-Reach (ELR) SerDes IP for TSMC 7nm/6nm operates at a full-rate of 112Gbps using PAM4 modulation and half-rate of 56Gbps using PAM4 modulation, as well as 56/28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The ELR PHY provides additional performance margin to highloss and reflective channels by incorporating reflection cancellation and enhanced digital signal processing. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links
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Block Diagram of the 112G-ELR PAM4 SerDes PHY
Serdes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency