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10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols
The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP has a lower-active and low leakage power design.
The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP has a lower-active and low leakage power design.
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Multi-protocol IP
- Multi-Protocol Crypto Packet Engine, Low Power, Bus Attached
- Multi-Protocol Crypto Engine
- Multi-Protocol Crypto Engine with Classification
- Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)