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10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
The first IP for PCIe 3.1 with L1 sub-states support
The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP is a lower-active and low leakage power design crafted for mobile, wireless IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR* , QSGMII, and SGMII specifications. The PCS complies with the PIPE 4.2 interfaces, and provides support for the dynamic equalization features of different protocols. The PHY IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to Cadence or third-party PIPE-compliant controllers.It provides a cost-effective, versatile, and low-power solution for demanding applications. It offers SoC integrators the advanced capabilities, flexibility, and support that meet the requirements of high-performance designs. The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.
The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP is a lower-active and low leakage power design crafted for mobile, wireless IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR* , QSGMII, and SGMII specifications. The PCS complies with the PIPE 4.2 interfaces, and provides support for the dynamic equalization features of different protocols. The PHY IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to Cadence or third-party PIPE-compliant controllers.It provides a cost-effective, versatile, and low-power solution for demanding applications. It offers SoC integrators the advanced capabilities, flexibility, and support that meet the requirements of high-performance designs. The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.
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PCIe 3.1 IP
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 4.0 Controller with AMBA AXI interface
- Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications