The world’s most reliable and mature full hardware
ultra-low latency TCP/IP, MAC and PCS IP Cores.
Bring the best-in-class ultra-low latency network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest latency improvements and optimizations.
- Management of layers 1, 2, 3 and 4 (OSI Model), compliant with
- Layer 1: IEEE802.3
- Layer 2: IEEE802.3, ARP (Address Resolution Protocol)
- Layer 3: IPv4 and ICMP (Internet Control Message Protocol)
- Layer 4: TCP (RFC 793)
- TCP Management per session
- Up to 128 simultaneous sessions
- Client or server mode configurable at runtime
- User Configurable TCP Options
- VLAN Priority, with insertion of PCP and DEI fields at emission
- Window Scale Factor
- Customizable MTU (Maximum Transmission Unit)
- Up to 9000 bytes payload to support from standard to jumbo frames
- MAC in Promiscuous mode (transparent)
- Access to MAC raw TX/RX interface
- ICMP and ARP protocol support
- Multiple Interface
- Up to 8 logical interfaces per instance
- Linked to any session
- VLAN configurable per interface
- Avalon/AXI-4 Streaming
- 128-bit wide interface running at 250 MHz for TCP/IP client port
- 64-bit wide interface running at 250 MHz for MAC client port (TCP/IP bypass)
- IP configuration/management
- 32-bit Avalon-MM/AXI- 4 lite slave control interface for MAC and TCP
- Status and statistics available for monitoring at MAC or TCP session level
- Customizable TCP retransmission buffer
- Customizable buffer size (depth and width)
- Customizable Internal or External memory support (DDRx, QDRx, …) depending configuration on performance and FPGA size requirements
- PHY Interface
- PMA Parallel Data between PCS and vendor PMA (PMA Direct Mode for Altera
- MII 64-bit Streaming Interface between PCS and MAC
- Best-in-class ultra-low latency from wire to user’s logic.
- 10G Ethernet connectivity. Maximum bandwidth delivered.
- Full RTL Layers 1, 2, 3 and 4, which include Enyx proprietary ultra-low latency full hardware TCP/IP, ARP, ICMP, MAC and PCS implementations.
- Clock configurable at up to 250 MHz, for improved latency results.
- Easy to use standardized Avalon and AXI-4 interfaces.
- Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique IPv4, MAC address, VLAN ID, Gateway and Mask.
- Up to 128 TCP sessions per instance, each of them configurable dynamically in server or client mode.
- nxTCP IP Core
- Libraries for functional simulation
- Synthesizable VHDL and Verilog RTL (encrypted) for synthesis/implementation
- nxTCP Testbench
- Client-Server Reference Designs
- Simulation environment and scripts
- Quartus II and Vivado Synthesis/implementation project for supported partner’s boards
- Complete Documentation
- User’s manual
- Getting started guide
- Technical Support and Maintenance Updates
- 1 year of technical support
- 1 year of IP updates
Block Diagram of the 10G Ultra-low latency TCP/IP + MAC + PCS IP core for FPGAs