10G Ultra-low latency TCP/IP + MAC + PCS IP core for FPGAs
ultra-low latency TCP/IP, MAC and PCS IP Cores.
Bring the best-in-class ultra-low latency network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest latency improvements and optimizations.
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Block Diagram of the 10G Ultra-low latency TCP/IP + MAC + PCS IP core for FPGAs
![10G Ultra-low latency TCP/IP + MAC + PCS IP core for FPGAs Block Diagam](http://www.design-reuse.com/sip/blockdiagram/41110/20161121031527-main-enyx.jpg)
TCP/IP + MAC IP
- 10G TCP Offload Engine+MAC+Host_IF Very Low Latency (XTOE)
- 10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe)
- 10G TCP Offload Engine+MAC+Host_IF Ultra-Low Latency (SXTOE)
- 10G TCP Offload Engine+MAC+PCIe+Host_IF Ultra-Low Latency (SXTOE+PCIe)
- 1G TCP Offload Engine TOE+MAC+Host_IF Ultra-Low Latency (STOE)
- 1G TCP Offload Engine TOE+MAC+PCIe+Host_IF Ultra-Low Latency (STOE+PCIe)