You are here:
10G Ultra Low latency, 32-bit MAC + PCS Solution (32-bit and 64-bit UI)
The 10Gbps 32-bit Ethernet IP solution offers a fully integrated IEEE802.3-2015 compliant package for NIC (Network Interface Card) and Ethernet switching applications. This industry leading ultra-low latency solution is specifically targeted for demanding financial, high frequency trading and HPC applications.
* Round Trip Latency of 52.7ns + Device Specific Transceiver Latency
As shown in the figure below, the 10Gbps Ethernet IP solution includes:
* Ultra-Low latency MAC; Tx = 12.4ns , Rx = 15.5ns; (32-bit user interface mode with FCS generation and checking)
* Ultra-Low latency PCS; Tx = 12.4ns , Rx = 12.4ns;
* Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs
* Statistics counter block (for RMON and MIB)
* MDIO and I2C cores for external module and optical module status/control
* Round Trip Latency of 52.7ns + Device Specific Transceiver Latency
As shown in the figure below, the 10Gbps Ethernet IP solution includes:
* Ultra-Low latency MAC; Tx = 12.4ns , Rx = 15.5ns; (32-bit user interface mode with FCS generation and checking)
* Ultra-Low latency PCS; Tx = 12.4ns , Rx = 12.4ns;
* Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs
* Statistics counter block (for RMON and MIB)
* MDIO and I2C cores for external module and optical module status/control
查看 10G Ultra Low latency, 32-bit MAC + PCS Solution (32-bit and 64-bit UI) 详细介绍：
- 查看 10G Ultra Low latency, 32-bit MAC + PCS Solution (32-bit and 64-bit UI) 完整数据手册
- 联系 10G Ultra Low latency, 32-bit MAC + PCS Solution (32-bit and 64-bit UI) 供应商
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E, N2P)
- 112G Ethernet PHY in TSMC (N7, N6, N5, N3P)
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency