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10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive
The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.
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PCI Express PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 5.0 SerDes PHY