You are here:
10G LL MAC/PCS IP Core
Chevin Technology's 10G LL MAC/PCS IP combines the XG MAC, Ultra Low- Latency 10-Gbit/s Ethernet MAC and XG PCS, PCS/PMA to optimize integration and performance of Ultra Low-Latency Ethernet connectivity in Xilinx FPGAs.
Designed to IEEE 802.3-2008; IEEE 802.3ae-2002 specifications, 10GBASE-R, the 10G LL MAC/PCS provides Ultra Low-Latency Ethernet connectivity with a RTT of 160 nanoseconds.
Get up and running quickly with the reference design on an AlphaData ADMPCIE KU3, or a Xilinx KC705 development board and a simple “ping” command line with the ICMP/ARP options. Use standard software TCP/UDP tools when integrated with the XGTCP IP block from Chevin Technology’s portfolio of IP blocks.
Designed to IEEE 802.3-2008; IEEE 802.3ae-2002 specifications, 10GBASE-R, the 10G LL MAC/PCS provides Ultra Low-Latency Ethernet connectivity with a RTT of 160 nanoseconds.
Get up and running quickly with the reference design on an AlphaData ADMPCIE KU3, or a Xilinx KC705 development board and a simple “ping” command line with the ICMP/ARP options. Use standard software TCP/UDP tools when integrated with the XGTCP IP block from Chevin Technology’s portfolio of IP blocks.
查看 10G LL MAC/PCS IP Core 详细介绍：
- 查看 10G LL MAC/PCS IP Core 完整数据手册
- 联系 10G LL MAC/PCS IP Core 供应商
Block Diagram of the 10G LL MAC/PCS IP Core
Ultra Low Latency IP
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- 5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
- 10G Ultra Low Latency Ethernet Solution
- 25G Ultra Low latency, 64-bit Ethernet MAC + PCS Solution (64-bit and 128-bit UI)
- 10G Ultra Low latency, 32-bit MAC + PCS Solution (32-bit and 64-bit UI)
- 40G Ethernet MAC/PCS Ultra Low Latency IP core for FPGAs