MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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100nA Ultra-low Power LDO in 110nm~12nm
The LDO IP supports various input voltage ranges include 1.90V~3.60V, 1.90V~5.50V and so on. The typical output voltage of this LDO can be configration.
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