The Xelic timesliced FLEXE Partial Shim Core (XCF124PS) supports 100G, 200G, and 400G FLEXE Aware Transport and FLEXE Termination Transport modes of operation and provides FLEXE OH frame alignment, multi-frame alignment, FLEXE Fail Signal insertion, overhead interpretation, error monitoring and consequential action support, and insertion/removal of unavailable calendar slots. Rate adaptation is achieved through interpretation of incoming FLEXE calendar information or through programmable provisioned slot configurations. The XCF124PS contains independent FLEXE Mapper and Demapper functionality with support for interfacing to OTN Timesliced FLEX Framer, Timesliced PCS Processor, and Timesliced Idle Mapping Procedure (IMP) modules.
The XCF124PS Timesliced FLEXE Mapper and Demapper align incoming FLEXE Shim data and extracts FLEXE overhead for interpretation. Performance Monitoring is provided with maskable interrupts for various error conditions including LOFL, MF error, LOMF, group number mismatch, PHY map mismatch, PHY number mismatch, and provisioned slots mismatch conditions. Performance counters are included for CRC-16 error detection along with programmable SSF and FAIL output signaling. Configurable FLEX Calendar slot insertion and removal is available for rate adaptation to transport in OTN FLEX Framer applications. Programmable FLEXE Fail Signal data is optionally generated for a variety of programmable error conditions. Incoming FLEXE overhead can be bypassed or overwritten through register control.
The XCF124PS implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between FLEXE Mapper and FLEXE Demapper modules with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.