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100 Gbit/s IEEE 802.3bj RS Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput. The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.
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Block Diagram of the 100 Gbit/s IEEE 802.3bj RS Encoder and Decoder
