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10 Gigabit Ethernet Media Access Controller (10GEMAC)
For UltraScale and UltraScale+ device support, refer to the 10G/25G Ethernet Subsystem
Designed to the IEEE 802.3-2012 specification
Xilinx provides a parameterizable LogiCORE™ IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. The core is designed to work with the latest Kintex® UltraScale™, Virtex® UltraScale, 7 Series, Virtex-6, Virtex-5 and Virtex-4 and Virtex-II Pro and Spartan®-6 platform FPGAs and integrate seamlessly into the Xilinx design flow.
The 10GEMAC core is designed to the IEEE 802.3-2012 specification and supports the high-bandwidth demands of network Internet Protocol (IP) traffic on LAN, MAN and WAN networks.
The Xilinx 10GEMAC core is another of the SystemIO solutions which provide high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The MAC core performs the Link function of the 10Gb Ethernet standard. The 10 Gigabit Media Independent Interface (XGMII) version of this core is intended to interface to either an off-chip PHY device or XAUI, DXAUI, RXAUI, 10GBASE-R/KR LogiCORE using the XGMII Interface.
Designed to the IEEE 802.3-2012 specification
Xilinx provides a parameterizable LogiCORE™ IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. The core is designed to work with the latest Kintex® UltraScale™, Virtex® UltraScale, 7 Series, Virtex-6, Virtex-5 and Virtex-4 and Virtex-II Pro and Spartan®-6 platform FPGAs and integrate seamlessly into the Xilinx design flow.
The 10GEMAC core is designed to the IEEE 802.3-2012 specification and supports the high-bandwidth demands of network Internet Protocol (IP) traffic on LAN, MAN and WAN networks.
The Xilinx 10GEMAC core is another of the SystemIO solutions which provide high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The MAC core performs the Link function of the 10Gb Ethernet standard. The 10 Gigabit Media Independent Interface (XGMII) version of this core is intended to interface to either an off-chip PHY device or XAUI, DXAUI, RXAUI, 10GBASE-R/KR LogiCORE using the XGMII Interface.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC