The S3DAIQ80M10BSM40LL employs a current steering architecture with differential current outputs. It uses 5 linear bits and 5 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
This 10-bit Dual DAC features an excellent static performance that includes ±0.8LSB DNL and ±2.0LSB INL for typical conditions.
Dynamic performance highlights considering a signal frequency of 10MHz and 80MS/s conversion rate include an SNR= 59dB and an SFDR>60dBc.
- 40nm SMIC LL Process, 6 Metals Used
- 3.3V and 1.1V Supplies
- Sampling Rate up to 80MS/s
- 0.8Vpp Differential Output Range
- DNL= 0.8LSB; INL<2.0LSB.Typ
- High Performance for Fout=20MHz
- Stand-By and Power-Down Modes
- 9mW Power Consumption at 1mA output current
- Area pre-shrink: 0.05mm2
- The S3DAIQ80M10BSM40LL is designed for operation up to 80MS/s. The S3DAIQ80M10BSM40LL is designed in a 40nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- WiFi 802.11x, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 10-Bit 80MS/s Dual Current Steering DAC