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Ridgetop Group’s 10-bit, 4 MS/s ADC core utilizes a pipeline architecture in the TSMC 0.25 μm process. The ADC converter design is 10-bit 4 MS/s, as shown in Figure 1.
The cell incorporates a 10-bit pipeline analogto- digital converter with up to five samplehold blocks. Four sample-hold blocks are used in parallel to sample input voltage and current. The fifth sample-hold block is used with the input multiplexer to provide up to eight auxiliary inputs. The cell also includes a current-to-voltage converter that converts current input signals to voltages.
10 bit 4Msps ADC in TSMC 0.25um
Ridgetop Group’s 10-bit, 4 MS/s ADC core utilizes a pipeline architecture in the TSMC 0.25 μm process. The ADC converter design is 10-bit 4 MS/s, as shown in Figure 1.
The cell incorporates a 10-bit pipeline analogto- digital converter with up to five samplehold blocks. Four sample-hold blocks are used in parallel to sample input voltage and current. The fifth sample-hold block is used with the input multiplexer to provide up to eight auxiliary inputs. The cell also includes a current-to-voltage converter that converts current input signals to voltages.
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