This DAC has been designed to reduce time to market, risk and cost in the development of Analog Front-Ends. A range of supporting IP blocks such as PLLs and A/D converters are also available.
- 10 Bit Resolution
- 400 MSPS Output Update Rate
- INL and DNL < 1 LSB
- 3.6nsec Settling Time (0.1% accuracy)
- Mid-code glitch energy < 10 pV-s
- Excellent distortion performance (SFDR>70dBc)
- 20mA full scale output current
- Core die area of 0.44mm2
- Power Dissipation < 80mW
- 3.3V/1.8V power supplies
- Scalable for lower resolution
- The INL and DNL is less than 1 LSB for both single ended and differential measurements.
- The settling time of the DAC is 3.6nsec (accurate to 0.1%)
- The measured glitch energy is less than 10 pV-s
- Very low output distortion: SFDR >60dBc at
- 400MSPS for Fin=20 MHz
- The core area of the DAC is 0.44mm2
- Developed on standard 0.18um logic process, the DAC is ideal for integration with a DSP engine. The DAC can be ported to any similar process.
- Lower power consumption can be achieved by increasing the external resistor size.
- The output voltage range can be set by selecting suitable load resistor or external bias resistor values. A single-ended output voltage range of 1V p-p is available.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Silicon Samples
- DemonstrationEvaluation Board
- Integration Support