GNSS (GPS, Galileo, GLONASS, Beidou3, QZSS, SBAS) Ultra-low power RF Receiver IP
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10-bit 1-channel constant power DAC
10-bit constant power DAC employs a current steering DAC architecture with control loop, which adjusts DAC input code to keep power dissipated in terminator constant. The block is easy to configure and operate, combining good accuracy and linearity. Several operation modes are available: constant power DAC, current DAC with output voltage monitoring, current DAC (manual mode), low-speed ADC. Output DAC current could be fed to one of two DAC outputs (DAC_OUT0 or DAC_OUT1) depending on Out_sel input. IP 250iHP_DAC_02 is modified version of previously designed Constant power DAC - 250iHP_DAC_01. Design modification was targeting change of output current polarity. In order to do this, following changes were made: pmos-type current mirrors 250iHP_CM_05a were added at outputs DAC_OUT0, DAC_OUT1; ADC inputs are separate pins now to probe voltage at outputs of 250iHP_CM_05a cells; ADC output is inverted to deal with changed output current and voltage polarity.
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