MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
10/100/1000 Tri-MAC 8-bit core with MII/GMII/RGMII interface @ 125MHz/25MHz/2.5MHz Solution
Tthe 10/100/1000Mbps MAC IP includes:
* AXI4-Streaming or Avalon-Streaming, FIFO based user side interface
* Triple speed MAC with MII/GMII PCS side interface and a simple FIFO based user side interface
* GMII to RGMII interface wrapper
* Statistics counter block (for RMON and MIB)
* MDIO cores for external PHY status/control
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