10/100/1Gbit MAC + AMBA Engine.
Highly customizable hardware IP block. Easily portable to Faraday-Tech’s structured ASIC flow, Xilinx or Altera FPGAs
INT-1000 is highly flexible that is customizable for layer-2 through Layer-7 network security and network infrastructure applications. It is recommended for use in, among others, high performance Network security appliances and Network infrastructure appliances. It provides the key IP building block for a single high performance Giga bit Ethernet ASIC/SOC/ASSP/FPGA.
INT-1000 provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others INT-1000 can process 1.4M packets for in-line in both directions, simultaneously, at full G-bit rate. The Direct write to Memory interface relieves the host CPU from costly DMA/buffer management execution and maintenance tasks.
- Ideal for high performance and mid performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications for sustained 1G, full-duplex (2G) at 100% utilization rate processing.
- Less than 40,000 ASIC gates + on-chip memory
- Fully integrated internal RAM block, synthesizable/selectable to 16KB-256KB
- 4 intelligent DMA engines.
- Direct Memory write and read control block, improves packet receive/transmit performance by 200-400%, by eliminating software driver to have to manage each frame and manage buffer pointers.
- Optional, On-chip DDR or SSRAM memory controller which can address 4K Bytes to 4 MB Bytes on chip or 256 MB off chip memories
- Separate User Data FIFO interface: 8/16/32/64 bit
- Host control interface: AMBA 2.0 (optional)
- Many trade-offs for some functions performed in hardware or software
- Configurable Packet Buffer size up to 256 KB for RX and TX.
- Automatic overflow into External Fast SSRAM. (optional)
- Jumbo frame support
- Same architecture scalable to 10Gbps.
- GMII or RGMII interface
- Sustained max packet transfer rate at 1G on Tx/Rx side;
- 64 - 1500 Byte packets at min IFG
- Special features for Hardware TCP/IP acceleration:
- TCP, UDP, and IP header checksum calculation for RX and TX
- Hardware header parsing for Ethernet v2/802.3/IPv4/IPv6/PPPoE
- TCP/IP header encapsulation and de-capsulation
- Zero-copy delay from MAC- FIFO to application buffer
- Fastest and most robust Ethernet MAC.
- Many features scalable
- Verilog source code or NetList.
- Verilog models for various components e.g. memory model EMAC, memory interface etc.
- Verification suite
- Test packet-traffic suite