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1 to 30 MHz Intermediate-Frequency Amplifier with Wide Gain Range
IFA consists of 3 stages amplifier with tunable gain, AGC system, linear buffer for analog output and an analog-digital converter (ADC) for 2-bits digital output and a detector of output level.
The amplifier has differential inputs and outputs. Gain is sequentially reduced from the last stage to the first stage. This method allows to keep a low noise figure in wide gain range.
In the analog output mode the circuit controls the gain so that the magnitude of the differential output signal. The signal level is set through Det_ampl_lvl<2:0>.
Digital output with AGC for analog signal mode operates similarly to the previous mode.
AGC operates in an automatic control mode of digital detector threshold for digital signal (MAGN). Threshold and gain are set by the DAC code. Digital output level is set 1.8V, 2.4V, 2.7V, ADC_VCC.
DC offset compensation system operates both at an amplifier output signal and at a buffer output signal.
The amplifier has differential inputs and outputs. Gain is sequentially reduced from the last stage to the first stage. This method allows to keep a low noise figure in wide gain range.
In the analog output mode the circuit controls the gain so that the magnitude of the differential output signal. The signal level is set through Det_ampl_lvl<2:0>.
Digital output with AGC for analog signal mode operates similarly to the previous mode.
AGC operates in an automatic control mode of digital detector threshold for digital signal (MAGN). Threshold and gain are set by the DAC code. Digital output level is set 1.8V, 2.4V, 2.7V, ADC_VCC.
DC offset compensation system operates both at an amplifier output signal and at a buffer output signal.
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