You are here:
1 Gbps LVDS Transmitter
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the transmitter. There are other two internal pins (VREF and BP_TX, BPC_TX, BN_TX) to get voltage reference and to gets voltage reference from transmitter bias. OUTP and OUTN are complementary outputs to connect to the bonding pads. LVDS transceiver cell may be used for half-duplex data transmission.
The LVDS transmitter is designed on iHP SiGe BiCMOS 0.13 um technology.
The LVDS transmitter is designed on iHP SiGe BiCMOS 0.13 um technology.
查看 1 Gbps LVDS Transmitter 详细介绍：
- 查看 1 Gbps LVDS Transmitter 完整数据手册
- 联系 1 Gbps LVDS Transmitter 供应商
LVDS Transmitter IP
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane
- MIPI D-PHY CSI-2 TX (Transmitter) in TowerJazz 65BSB
- IGALVDV05A, TSMC CLN12FFC 6-Channel LVDS Transmitter PHY
- LVDS 10 bits dual port transmitter