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Programmable LVDS Transmitter/Receiver - TSMC 90nm
The LVDS circuit consists of transmitter (LVDSOUT), receiver (LVDSIN) and bias. The LVDS transmitter consists of a current source (nominal 3.5 mA) that drives the differential pair lines and common-mode regulator that provides the output common-mode voltage signal equal 1.25 V. The output current adjustment is defined by the digital code register ilvo<2:0>. The receiver has high DC input impedance (~MΩ), so the majority of driver current flows across the 100 Ω external termination resistor generating about 350 mV across the receiver inputs. When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid “one” or “zero” logic state. That is it transforms input 350 mV signal to CMOS 1.8 V output signal. The internal current adjustment is defined by digital code register ilvi<2:0>.
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LVDS IP
- TSMC GF LVDS Tx/Rx with optional CMOS I/O
- TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF