MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
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1.5-GHz Jitter-optimized low-power digital PLL
The DeepSub pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator and pDIV post-scaler. pPLL03 is currently in silicon in the Silterra 180G and GlobalFoundries 65LPe processes.
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