MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
1.2V/1.8V/2.5V Capable Fail Safe General Purpose IO (GPIO) (CDM5A/7A-ESD) - TSMC 5nm 5FF
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interface IP IP
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