MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
1.25 Gbps EPON SerDes IP
The receiver side implements programmable post-equalization, with on chip terminations, clock/data recovery PLL and De-Serializer. The Serializer section uses the recovered clock to serialize the parallel data to be transmitted. The transmitter then drives the serial data on the serial differential outputs, while incorporating the pre-emphasis signal.
The MXL-SRDS-EPON is capable of generating low-jitter outputs in the noisy environment typical of million-gate SOC.
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