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1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in TSMC 65nm
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain cells, 3.3V & 5V analog cells, OTP program cell & associated ESD
Key attributes of this IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in HiZ during power-down. The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and optional internal 55K ohm pull-up or pull-down resistor. Cells for two independent IO supplies, core power, ground and isolated ground with built-in ESD are included. A specialty output cell with matched throughput timings for pulse-width modulation (PWM) applications, along with 5V OTP programming, I2C & SVID open-drain and 3.3V & 5V analog cells (and associated ESD) complement the GPIO offering. The library is enriched with filler, corner, and domain-break cells in digital and analog domains, allowing for flexible pad ring construction. ESD design levels are 2KV HBM and 500V CDM
Key attributes of this IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in HiZ during power-down. The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and optional internal 55K ohm pull-up or pull-down resistor. Cells for two independent IO supplies, core power, ground and isolated ground with built-in ESD are included. A specialty output cell with matched throughput timings for pulse-width modulation (PWM) applications, along with 5V OTP programming, I2C & SVID open-drain and 3.3V & 5V analog cells (and associated ESD) complement the GPIO offering. The library is enriched with filler, corner, and domain-break cells in digital and analog domains, allowing for flexible pad ring construction. ESD design levels are 2KV HBM and 500V CDM
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Block Diagram of the 1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in TSMC 65nm
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