YorChip推出低延迟 100G ULTRA 以太网就绪 MAC/PCS IP, 助力边缘 AI

YorChip, Inc. in collaboration with its design partner SiliconIPs announces development of a 50nS latency 100G Ultra Ethernet ready Mac/PCS IP core.

SAN RAMON, CA, UNITED STATES, February 19, 2025 -- YorChip, Inc. in collaboration with its design partner SiliconIPs announces development of a 50nS latency 100G Ultra Ethernet ready Mac/PCS IP core. The IP is optimized for size, power and latency and targets edge AI applications as well as Data Center Accelerator developers needing low power and latency. The IP is optimized to work with leading FEC cores from IP Cores Inc. to deliver the lowest latency in the market. YorChip plans to develop Chiplets for edge markets and to license the IP to a broad range of developers world-wide.

Chiplets represents multi-billion-dollar market potential – according to Transparency Market Research, the Chiplet market is expected to reach more than US$47 Billion by 2031, representing one of the fastest growing segments of the semiconductor industry at more than 40% CAGR from 2021 to 2031. This growth was expected to be enabled by the considerable cost reduction and improved yields Chiplets will enable as compared to traditional system-on-chip (SOC) designs but has been limited by high packaging and PHY costs to HPC markets.

YorChip’s CEO and founder, Kash Johal, said, “Ethernet is about to have its day in AI with the new forthcoming Ultra Ethernet standard and we expect a broad range of markets needing low power, low latency solutions. This 100G IP is optimized for low power coupled with low latency with ability to support the latest standards. AI acceleration for 100G and 200G data streams is a key niche market we can enable with this new solution. And best of all there is no Vendor Lock-in to a specific SERDES vendor, and designers can use the best-in-class MAC/PCS with any SERDES of their choice.”

YorChip’s CTO and founder, Frank Dunlap said, “For developers needing to run with lowest latency we can run over 4 lanes of 25G NRZ without a FEC and delivering 50nS round trip latency. This non-standard mode is optimal for cost-sensitive edge-AI applications. Multiple FEC options can also be deployed with best in class latency for higher bandwidth requirements.”

Alex Tesler, CEO of IP Cores said “We have had Reed Solomon FEC cores for many years and they are silicon proven in many nodes. It is an exciting time in the industry as Ethernet now extends to AI connectivity with low latency and deterministic delivery using Ultra Ethernet.”

Availability

Now for design in.

About YorChip

We are a Silicon Valley start-up with patent-pending technology for programmable Chiplet PHY technology. We offer intellectual property licensing and also plan to offer Chiplets for re-sale to end customers across a broad range of markets by leveraging our Universal PHY and advanced packaging technology. YorChip is headquartered in San Ramon, California with design partners worldwide.

About SiliconIPs

SiliconIPs is a stealth start-up based in Silicon Valley focused on low power, low latency interconnect.

About IP Cores

IP Cores is a successful company based in Silicon Valley developing communication, security and other IP cores.