New open standard RISC-V Verification Interface (RVVI) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification
Oxford, United Kingdom, March 1st, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the official 1.0 release of the new RVVI (RISC-V Verification Interface) as a foundation for the new RISC-V verification ecosystem. The open standard ISA (Instruction Set Architecture) of RISC-V has stimulated the interest in optimized processors across almost all market segment and application areas. Since previously SoC developers were constrained to consider only a few limited mainstream IP cores, the design freedom of RISC-V has generated significant interest for innovation. This design freedom is also migrating the verification responsibility from a few IP providers to all adopters that choose to exploit these new design freedoms of RISC-V.
The key ecosystems for successful mass market processor adoption have previously focused on software (such as development tools, compilers, and operating systems), and hardware (EDA tools for RTL simulation, gate level synthesis, and physical layout). While all ISA’s have many unique and special features, these dual ecosystems of hardware and software have supported them all. However, since previous processor IP cores were all single sourced, the verification task was performed in house with techniques closely guarded as trade secrets. In addition, since ‘known-good’ processor IP was the base assumption for all SoC verification flows, the processor IP cores were not tested by the SoC adopters. Now with RISC-V, as an open standard ISA, any developer can explore the full range of the design features offered by the ISA specification. Thus, in turn, all adopters that choose to extend, modify or build a custom processor core will also need to address the design verification (DV) requirements.
Imperas recently announced the ImperasDV solution with a combination of a quality reference model, test suites and verification methodology to address the full spectrum of RISC-V implementations. The RTL of the device under test (DUT) is typically set-up with a test bench to control and monitor the operational analysis during the verification process. The test bench needs to support all the features of the core, including the specialist DV tasks for test and analysis with debug operations. As the test bench interfaces to the processor RTL (DUT), test generators, reference model, verification IP, and the EDA tools for RTL simulation, any errors or admissions have a significant impact on the quality of the testing and could allow errors to escape unnoticed into late stages of the design, silicon prototypes, or even production devices. While a custom test bench could be created for any target DUT, this approach limits the options for reuse and leverage other components that could save time and effort. The new RVVI open standard and methodology, is based on an open specification (see this link on GitHub) and can be adapted to any configuration permitted within the RISC-V specifications. In adopting the RVVI standard, developers can leverage all the common components off the shelf and explore additional options with 3rd party Verification IP. In addition, since many projects evolve into further enhancements for successor designs, the investment in the verification infrastructure can be reused for both future core projects and ongoing regression frameworks.
RVVI technical summary & highlights
- New open standard RVVI (RISC-V Verification Interface) provides:
- Seamless integration between RTL, reference model and testbench
- Close-coupled integration for instruction accurate lock-step-and-compare
- Supports multi-hart, superscalar and out-of-order CPU pipelines
- Fully compliant with the standards for UVM
- SystemVerilog integration compatible with the tools and environments offered by Cadence, Siemens EDA, Synopsys, and the Metrics cloud-based tools.
The new RVVI (RISC-V Verification Interface) is an open standard developed by Imperas with guidance and support from lead customers and users, is available now, and is being adopted by the RISC-V test and verification community: https://github.com/riscv-verification/RVVI.
“The OpenHW Verification Task Group contributors are pioneers in the drive to advance the quality of open-source hardware IP ready for mainstream adoption – quality deliverables are the hallmark of any trusted IP provider, commercial or open source,” said Rick O’Connor, President & CEO OpenHW Group. “OpenHW membership growth over the past three years is expanding the roadmap of IP core projects dramatically, with projects addressing the needs for application class devices supporting Linux, embedded security, and compute intensive applications with custom instructions. The RVVI open standard and flexible methodology significantly helps the OpenHW Verification Task Group members and contributors with efficient and quality verification for the full range of CORE-V IP projects.”
“We are at the epicentre of the biggest migration of verification responsibility in the history of processor IP and EDA tools,” said Simon Davidmann, CEO at Imperas Software Ltd. “Now every SoC design team can embrace the processor design flexibility of RISC-V for optimized domain specific solutions – but this marks the end of the ‘one-size-fits-all’ era of processor IP. Expanding the scope of the established SoC verification flows to accommodate the additional complexity of RISC-V processor DV is defining the new verification ecosystem, which is unique for the adopters of the RISC-V ISA.”
The RVVI (RISC-V Verification Interface) specification is available at https://github.com/riscv-verification/RVVI.
The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high performance computing. A select sample of these include - Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.
ImperasDV is available now, more details are available at Imperas.com/ImperasDV.
The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is also available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.
Imperas will host a deep-dive technical tutorial on RVVI as part of ‘Introduction to the 5 levels of RISC-V Processor Verification’ at DVCon 2022, in addition to talks and presentation on the latest trends and developments for RISC-V Verification. More details on the tutorial, talks, and to request a demo are available at this link.
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
For more information about Imperas, please see www.imperas.com.