June 30, 2021 -- System Level Solutions is serving USB IP core solutions for Intel and Microsemi FPGA platform since 16 years. From good response of customers globally as well as looking at market requirement, SLS USB 2.0 Device Controller IP core is now available to Lattice Semiconductor FPGA platform.
Universal Serial Bus or USB has been around for a long time and it is useful to connect a wide variety of devices from storage to input hardware. The purpose of USB is to connect external devices easily by creating a standardized connector to replace the multitude of connectors in the product.
IP core Key Features:
- Supports LS (1.5 Mbps)*, FS (12 Mbps) and HS (480 Mbps) modes
- Supports Control, Bulk, Interrupt and Isochronous transfers
- Capable to support up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints)
- Supports software configurable endpoints
- Allows you to configure endpoints based on your needs
- Supports Suspend, Resume and Remote Wakeup features
- Supports Test modes (Test J, Test K, Test SE0 NAK, Test Packet)
- Ready to use component
- Simple FIFO interface to transfer data over non-control endpoint
IP core Verification:
- USB 2.0 Device Controller IP core’s functionality is verified in ModelSim simulation software using test bench written in Verilog HDL
- The IP Core is tested with various USB 2.0 PHY Chip
Useful to connect end devices like:
- Sensor system
- USB Mass Storage
- Many more
For quick prototype and reduced design cycle, SLS provides IP core along with add-ons such as License for encrypted IP core, Reference design, Demonstration, Software bundle, Technical documents. Of course, SLS helps their customers by providing pre and post sales technical support for generating programming file and other things.
For more information and price details, please write us at firstname.lastname@example.org