SiFive 的Performance P550 内核树立RISC-V 处理器 IP 最高性能新标准

New SiFive Performance Family of application processors offers best in class performance, area, and efficiency for a wide variety of markets

SAN MATEO, Calif., June 22, 2021 – SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, today announced launched the new SiFive Performance family of processors. The SiFive Performance family debuts with two new processor cores, the P270, SiFive’s first Linux capable processor with full support for the RISC-V vector extension v1.0 rc, and the SiFive Performance P550 core, SiFive’s highest performance processor to date. The new SiFive Performance P550 delivers a SPECInt 2006 score of 8.65/GHz, making it the highest performance RISC-V processor available today, and comparable to existing proprietary solutions in the application processor space.

“SiFive Performance is a significant milestone in our commitment to deliver a complete, scalable portfolio of RISC-V cores to customers in all markets who are at the vanguard of SOC design and are dissatisfied with the status quo,” said Dr. Yunsup Lee, Co-Founder and CTO of SiFive. “These two new products cover new performance points and a wide range of application areas, from efficient vector processors that easily displace yesterday’s SIMD architectures, to the bleeding edge that the P550 represents. SiFive is proud to set the standard for RISC-V processing and is ready to deliver these products to customers today.”

“We are pleased to be a lead development partner with SiFive to showcase to mutual customers the impressive performance of their P550 on our 7nm Horse Creek platform," said Amber Huffman, Intel Fellow and CTO of IP engineering group at Intel. "By combining Intel's leading-edge interface IP such as DDR and PCIe with SiFive's highest performance processor, Horse Creek will provide a valuable and expandable development vehicle for cutting-edge RISC-V applications."

“Growing from its initial success in embedded processors to tackle the application processor market requires the performance, efficiency, and features demonstrated in the new SiFive Performance P550 core,” said Kevin Krewell, Principal Analyst, TIRIAS Research. “Combined with the maturing and growing open-source software ecosystem for RISC-V developed by leading technology industry companies, chip designers have a real choice for their next SoC application processor core.”

The SiFive Performance P550 features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GC ISA. Evolved from the previously announced SiFive U84 microarchitecture, Performance P550 scales up to four-core complex configurations that use a similar amount of area as a single Arm Cortex-A75 while delivering a significant performance-per-area advantage.

The SiFive Performance P270 is an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA. With full support for the RISC-V Vector Extension v 1.0RC, and combined with SiFive Recode, which translates existing SIMD software from popular legacy architectures to RISC-V Vector assembly code, the SiFive Performance P270 is an ideal replacement for dated SIMD architectures.

The new SiFive Performance family joins the recently announced SiFive Intelligence family that is focused on AI & ML applications, and the broadly adopted SiFive Essential family of configurable cores that includes the U/S/E-Series of 64-bit and 32-bit processors.

For more on the complete SiFive processor portfolio, see CEO Patrick Little’s blog here. Both products in the SiFive Performance family are available now. SiFive will conduct a webinar with details about the SiFive Performance, Intelligence, and Essential product families on July 14th with registration available here.

About SiFive

SiFive is the leading provider of processor cores, AI accelerators, and SoC IP to enable domain-specific designs based on the open RISC-V instruction set architecture specification. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit www.sifive.com.