RISC-V Vector Instruction Extension for Automotive applications to be verified with Imperas leading proprietary code-morphing simulation technology, verification tools and validation suite
Oxford, United Kingdom, September 24th, 2020 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today confirmed the selection by NSITEXE, Inc., a group company of the DENSO Corporation that develops and sells high-performance semiconductor IPs, for the development and verification of the next generation Automotive processor IP based on RISC-V with vector instruction extension. RISC-V is an open ISA (Instruction Set Architecture), which permits many configurations and options for processor implementation and microarchitectural features. The vector instruction extensions support complex arithmetic operations required for applications involving linear algebra, such as AI (Artificial Intelligence) and ML (Machine Learning). Extensive test and verification is required to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles.
Virtual Platforms based on Imperas models and simulator allow early SoC architectural exploration as system developers map complex AI algorithms to new multiprocessor configurations. As RISC-V supports both standard instruction extensions such as vectors, as well as user defined custom instructions, the Imperas models and analysis tools support the complete flexibility and design freedoms for the front-end design flow. As the project develops to the next phase, the hardware design verification (DV) team can use the Imperas RISC-V reference model and verification suite to validate the design before tape-out. Due to the broad range of configurations available for the vector extensions the Imperas verification suite includes a compliance validation test to ensure early compatibility with the growing ecosystem supporting RISC-V vectors.
“For the automotive market our customers expect the highest standards of quality and design assurance,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation. “NSITEXE selected the Imperas Vector Extensions Compliance test cases and RISC-V Reference Model as a foundation for our simulation-based design verification (DV) plans.”
“Virtual platforms enable the essential early development of software well before RTL or silicon prototypes are available, which dramatically accelerates the time to market,” said Nobuyuki Ueyama, President of eSOL TRINITY Co., Ltd. “In addition, for the next generation of automotive AI designs, the early architectural exploration of the SoC helps validate the system design and becomes the reference model for RTL verification.”
“The RISC-V vector instruction extensions offer a broad set of parameterizable features, functions and options that can be fine-tuned for the target application,” said Simon Davidmann, CEO at Imperas Software Ltd. “Two of the most critical requirements of a professional DV plan are the reference model for functional verification and test suite for validation and ecosystem compliance. We are proud to support the engineering team at NSITEXE with the Imperas golden reference model for RISC-V, including vector extensions.”
The latest RISC-V vector instruction extension specification is fully implemented within the Imperas RISC-V reference model. riscvOVPsim is a free single-core model and simulator which is available on GitHub for both commercial and non-commercial use at https://github.com/riscv/riscv-ovpsim. riscvOVPsim is also the reference model as used by the RISC-V International Compliance working group developing the official reference compliance suite which will be used by all implementers, adopters and ecosystem partners. The latest official compliance suite is available at: https://github.com/riscv/riscv-compliance.
Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.