Breker Verification Systems推出独竖一帜的RISC-V TrekApp解决方案，适用于自动化、高覆盖率系统集成测试综合套件

Developed with SiFive to Address RISC-V System Integration Validation; Generates High-Impact SoC Verification Test Suite with Minimal Manual Effort

SAN JOSE, CALIF. –– December 10, 2019 –– Breker Verification Systems, the leading provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), today introduced its RISC-V TrekApp, a complete, automated test content generator for RISC-V system integration testing.

RISC-V TrekApp, the first solution to address the entire RISC-V system-on-chip (SoC) system integration problem, targets complex verification challenges and increases coverage by executing unpredictable corner-case scenarios without the need for manually developed test content. The TrekApp works with existing universal verification methodology (UVM) and SoC verification environments and does not require the user to learn the PSS language.

“RISC-V excels in enabling new and innovative designs, creating verification opportunities for system integration,” remarks Adnan Hamid, Breker’s president and chief executive officer. “Breker’s RISC-V TrekApp builds on our success with other processors to fully automate this intensive task while allowing for the distinctiveness created by RISC-V, saving hours of laborious test development while increasing coverage.”

The RISC-V TrekApp was developed in cooperation with SiFive, the leading provider of commercial RISC-V processor IP and silicon solutions, and was validated first on SiFive processors. It is also in use by multiple processor developers to test the integration of their custom devices.

“Working with Breker to develop the RISC-V TrekApp over the past year has been very rewarding,” says Mohit Gupta, vice president and general manager of the SiFive IP business unit. “As RISC-V adoption continues to grow, support from design tool providers like Breker is key to accelerating time to market and assuring SoC quality.”

The RISC-V TrekApp Advantage

Breker’s new TrekApp provides a complete system integration test for RISC-V processors using Test Suite Synthesis. A configurable test content generator for UVM and Software Driven Verification (SDV) environments, it targets a range of subsystem verification challenges that otherwise require months of manual test authoring. It enables users to integrate a compliant RISC-V processor onto an SoC platform and perform all necessary tests to ensure the platform is ready to run without the need to learn the PSS language.

Features include interrupt mechanism testing, modular instruction extension verification and links to multiple compliance test suites. A comprehensive full debug environment highlights tests that fail, including memory map and key register detail, and interfaces with common debuggers such as Synopsys’ Verdi® SoC Debug Platform for extended analysis.

SoC operational profiling is accomplished using the TrekApp by scheduling many multi-threaded tests together. This allows design performance and power analysis for an early indication of general design operation. Extensive coverage information reveals how much of the subsystem functionality was tested and permits coverage-directed test generation for high-impact verification.

RISC-V TrekApp results can be combined with general functional verification tests written in PSS, SystemVerilog, UVM, SystemC and C/C++ for a complete, cross-coverage test environment. It does not require knowledge of PSS, SystemVerilog or UVM languages and may be used in a fully automated fashion.

The RISC-V TrekApp can be used with other TrekApps such as Power Domain, Security and additional common SoC verification functions. It operates on all standard simulators, emulators, rapid prototyping systems and virtual platforms, as well as post-silicon validation environments.

A cache coherency test suite enables automated systematic testing of data consistency and cache state transitions across all caches (L1/L2/L3 snoop filters) for multi-core/multi-cluster designs with I/O coherent interfaces such as PCI Express. Integration with fabrics, memory controllers (DDR and HBM) are stress tested as are atomic and other special memory accesses. For instruction extension verification, verification tests can be written in PSS, SystemVerilog, UVM and/or C/C++. These tests can be easily amalgamated with the system integration test suite for complete, diverse scenario examination to confirm that no additional instructions will impair smooth operation of the SoC.

Breker’s RISC-V TrekApp is available now as part of the Breker Trek5 product suite. Pricing is available upon request.

Breker at the RISC-V Summit

Dave Kelf, Breker’s vice president and chief marketing officer, will participate in “The RISC-V Open ISA’s shock Wave of Processor Innovation that’s Causing a Seismic Shift in SoC Verification Requirements” panel during the RISC-V Summit. It will be held Tuesday, December 10, from 2:20 p.m. until 3:10 p.m. at the San Jose Convention Center in San Jose, Calif.

About Breker Verification Systems

Breker Verification Systems is the leading provider of Test Suite Synthesis tools leveraging Portable Stimulus, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from abstract scenario models. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, to produce optimized tests for UVM, SoC and other environments, and Shareable, eliminating test redundancy across the verification process and to foster team communication and reuse. Breker’s testbench synthesis suite of tools and TrekApps allows optimization of high-coverage, powerful test cases for deployment into a variety of UVM to SoC verification environments. Breker is privately held and works with leading semiconductor companies worldwide.