RISC-V 基金会宣布批准RISC-V Base ISA以及特权架构规范

Ratification marks a milestone for the growing RISC-V ecosystem

BERKELEY, Calif.-- July 10, 2019 -- The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the ratification of the RISC-V base ISA and privileged architecture specifications. The RISC-V base architecture is the interface between application software and hardware. Software that’s coded to this specification will continue to work on RISC-V processors in perpetuity, even as the architecture evolves through the development of new extensions.

“RISC-V was designed with a simple fixed base ISA and modular fixed standard extensions to help prevent fragmentation while also supporting customization,” said Krste Asanović, chairman of the RISC-V Foundation Board of Directors. “The RISC-V ecosystem has already demonstrated a large degree of interoperability among various implementations. Now that the base architecture has been ratified, developers can be assured that their software written for RISC-V will run on all similar RISC-V cores forever.”

Privilege levels are used to provide protection between different components of the software stack, and attempts to perform operations not permitted by the current privilege mode will cause an exception to be raised. The RISC-V privileged architecture covers all aspects of RISC-V systems beyond the unprivileged ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices. Each privilege level has a core set of privileged ISA extensions with optional extensions and variants, including the machine ISA, supervisor ISA and hypervisor ISA.

“The RISC-V privileged architecture serves as a contract between RISC-V hardware and software such as Linux and FreeBSD. Ratifying these standards is a milestone for RISC-V,” said Andrew Waterman, chair of the RISC-V Privileged Architecture Task Group. “Operating system developers and hardware vendors can build to these specs with confidence that their work will be compatible.”

The RISC-V Foundation has seen significant growth over the past few years with more than 275 organizations, individuals, and universities from 28 countries and six continents around the world. The RISC-V ISA has already witnessed rising commercial adoption and implementations across a variety of industries.

To check out the RISC-V specification, please visit: https://riscv.org/specifications/privileged-isa/.

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 275 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.