TEWKSBURY, MA. -- May 30, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimCluster GLS that performs gate-level parallel simulation to achieve 3-5X speed up of sign-off simulations.
“As chips get larger the feasibility of performing post-layout SDF-based gate-level simulation gets harder and harder,” said Chris Browy, VP Sales/Marketing. SimCluster GLS performs scalable parallel simulation using VCS, Xcelium, or Questa in either multi-core and datacenter cluster compute environments to simulate faster and shrink turn-around times on sign-off simulations.
Highlights of the new SimCluster GLS solution:
- No design changes, no testbench changes, no SDF changes
- Engines run with cycle-based or lock-step synchronization
- Supports all three major simulators (Xcelium/VCS/Questa)
- Simulation analyzer tool generates design block workload, port change activities, interconnect complexity between blocks, synchronization analysis, and design hierarchy report
- Automatic coarse-grained partitioning of flat and hierarchical netlists
- Patent pending methods further optimize performance
Visit us at the Design Automation Conference in Las Vegas during June 2-6.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.