TEWKSBURY, MA. -- May 31, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SymXprop that performs high accuracy semi-formal based RTL X handling to eliminate the inherent inaccuracies in logic simulators.
“Design practices involving partial reset, uninitialized memories, and clock and power gating expose SystemVerilog’s inaccurate RTL X handling semantics by creating X-optimism and X-pessimism issues in RTL simulations and result in extra engineering time needed to effectively debug and work around the issues,” said Chris Browy, VP Sales/Marketing. SymXprop analyzes X propagations in RTL simulations for combinatorial and sequential X inaccuracies using patent pending hybrid formal analysis and automatically eliminates these X inaccuracies in RTL simulations.
Highlights of the new SymXprop solution:
- Analysis modes for X-optimism and X-pessimism
- Scalable to large designs with built-in distributed parallel processing
- Analyze one or multiple submodules displaying X issues
- Supports VCS, Xcelium, and Questa simulators
Visit us at the Design Automation Conference in Las Vegas during June 2-6.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.