The new release of the Multifunction IP Core for Xilinx 7 series FPGAs is based on the Xilinx Hard IP block for PCI Express and maps AXI Masters to the individual PCI Functions.
Hildrizhausen, Germany, September 12, 2018 – Smartlogic today announced the immediate availability of the new 2.0 Release of the Multifunction IP Core for PCI Express®.
The PCI Express® Specification allows Devices that incorporate more than one physical PCI Function. Such Devices are known as Multi-Function Devices. The advantage of a Multi-Function Device is, that separate device drivers can be associated to each physical function. This simplifies driver development and maintenance significantly by separating different peripheral functions logically into different device drivers.
The Xilinx PCIe Hardblocks in the Xilinx 7 Series FPGA Device family however do not support more than one physical PCIe Function and do not support Multi-Function Devices natively.
"Our patented approach by extending the Xilinx PCI Express Hard IP Block with up to 6 individual PCI Functions uses significant less logic resources than a dedicated Multifunction Soft IP Core", said Thomas Zerrer, CEO of Smartlogic. "Therefore our solution fits even in very small Artix Devices."
For easy integration into customer designs, the IP Core provides up to 6 AXI Masters Interfaces that can be mapped individually at compile time to Functions and their BARs.
The IP Core is also featuring a link stability detector that continuously monitors data failures caused by signal integrity issues. This information can be used during production testing or at runtime.
Visit Smartlogic’s Website (https://smartlogic.de/en/our-range-of-services/dma-ip-cores-for-pci-express/) to download the datasheet and a block diagram.