TEWKSBURY, Mass.– August 06, 2018 - Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced integration of the company’s flagship PCI Express® (PCIe®) and NVM Express® (NVMe) VIP solutions with Teledyne LeCroy Summit Z3-16™and Z416™ Protocol Exercisers enabling post-silicon, at-speed bring-up and validation and debug of PCIe 4.0 and NVMe 1.3 SSD designs using traffic generation files automatically converted from selected SystemVerilog/UVM testcases running in the RTL simulation and emulation.
Functional verification testcases developed using the PCIe and NVMe VIP for RTL and netlist-level simulation or emulation verification environments, including the compliance testsuites offered by Avery, can now be selectively targeted and generated in the Summit PETrainerTM scripting language for Summit Z3-16 and Z416 Protocol Exercisers including support for key exerciser features such as PCIe and NVMe Host Emulation modes, error injection, link and PHY controls such as lane skew, speed change, and low power states transitions. Full BIOS enumeration and NVMe discovery and initialization steps are supported in the generated PETrainer scripts because they are also fully supported by the PCIe and NVMe VIP. Design validation is performed through generating and comparing the end-state memory signatures between the RTL simulation/emulation and at-speed exerciser runs of the PCIe Configuration and NVMe Controller registers and memory spaces further ensuring design operation is consistent from RTL to silicon.
“The power and flexibility of the Avery PCIe and NVMe VIP for creating highly randomized DUT configuration and PHY layer parameters and randomized PCIe traffic sequences and PRP and SGL generation for NVMe designs provides a level of all layer stress testing that can be difficult to create using traditional application-level testing based on standard OS, drivers, and motherboard-based testing,” said Chris Browy, vice president of sales/marketing at Avery. “Using Avery VIP with Summit protocol exercisers in this manner enables being able to develop, run, verify, and debug these tests in reference RTL simulation first and then directly bring the PETrainer scripts to the protocol exerciser to run and analyze the results on actual silicon. The overall process of writing tests and debug is more direct, flexible, and productive at the same time. Avery plans to support additional protocols in the future.”
Visit Avery at Flash Memory Summit 2018 August 7-9, 2018 at the Santa Clara Convention Center in Santa Clara, CA.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, GDDR, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, Ethernet, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.