PALO ALTO, Calif.-- June 04, 2018 -- IP Cores, Inc., (California, USA, http://www.ipcores.com) has announced modifications of its MSP10-512 cores that support line-speed MACsec encryption and decryption for the 400 Gbps Ethernet.
“Our successful MSP10 MACsec core family has been upgraded to reduce the footprint in the ASICs utilizing advanced semiconductor nodes,” said Dmitri Varsanofiev, CTO of IP Cores, Inc. “The core is fully integrated with secure association context lookup and MACsec header parsing, validation, insertion, and removal.”
MSP10 400 Gbps Ethernet Encryption Core
MSP10 MACsec IP core delivers full 400 Gbps data rate on any frame mix, including the shortest 64-byte Ethernet frames. Variety of the core configurations permits up to tens of thousands of concurrently active secure associations. All popular features of the upcoming revision of the IEEE 801.1AE MACsec standard are supported, including the 64-bit extended packet numbering (a.k.a. IEEE 802.1AEbw, XPN) and GCM-AES-256 encryption (a.k.a. IEEE 801.1AEbn). MSP10 IP cores support channelization (a.k.a. fracturability, ability to process in time-multiplexed fashion, for example 1x400 Gbps stream, 2x200 Gbps, 1x200 + 1x100 + 2x50 Gbps, etc.).
IP cores from the MSP10 family have been available for many years for ASICs and all modern FPGA families, including those manufactured by Altera and Xilinx, see the details at http://www.ipcores.com/msp10_macsec_processor_ip_core.htm
MACsec is the IEEE MAC Security standard (also known as 802.1AE, https://1.ieee802.org/security/802-1ae/) that defines connectionless data confidentiality and integrity for media access protocols. It is standardized by the IEEE 802.1 working group. MACsec specifies the implementation of a MAC Security Entities (SecY) and defines MACsec frame format, which is similar to the Ethernet frame, but includes additional fields (Security Tag and Message authentication code or ICV).
MACsec uses Galois/Counter Mode of Advanced Encryption Standard cipher with 128-bit key (AES-GCM-128) as a default cipher suite.
Security tag inside each frame in addition to Ethertype includes association number within the channel and packet number to provide unique initialization vector for encryption and authentication algorithms as well as protection against replay attack as well as the secure channel identifier.
About IP Cores, Inc.
IP Cores (http://www.ipcores.com) is a rapidly growing California company in the field of security, error correction, data compression, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for embedded, communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, MACsec 802.1AE, IPsec and SSL/TLS protocol processors, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure cryptographic hashes (SHA-1/MD5, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), lossless data compression cores, low-latency and low-power fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi forward error correction (FEC) decoder cores.