IP Cores宣布发布32位版本的超低功耗FFT IP核

PALO ALTO, Calif. -- May 23, 2018 -- IP Cores, Inc., California, USA (http://www.ipcores.com) has announced shipment of a 32-bit core from its popular low-power FFT core family, FFT1.

“Our popular low-power FFT1 core family now includes a high-accuracy 32-bit core FFT1-32,” said Dmitri Varsanofiev, CTO of IP Cores, Inc. “The core delivers the similar microwatts-level power consumption as the original 16-bits-and-below versions. To further reduce the power consumption the FFT1-32 is capable of running with the reduced precision if lower accuracy is required by an application”.

FFT1 FFT/IFFT IP Core Family

IP cores from the FFT1 family are targeting the low-power always-on applications, for example, offloading the processing of the acoustic and acceleration sensors. The standard features include the use of single-port RAM and support for block floating point. To further reduce the power consumption of the microprocessor, FFT1 cores are capable of offloading application-specific vector operations.

IP cores from the FFT1 family have been available for many years primarily for ASICs (FPGA versions are also available).

About IP Cores, Inc.

IP Cores (http://www.ipcores.com) is a rapidly growing California company in the field of security, error correction, data compression, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for embedded, communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, MACsec 802.1AE, IPsec and SSL/TLS protocol processors, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure cryptographic hashes (SHA-1/MD5, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), lossless data compression cores, low-latency and low-power fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi forward error correction (FEC) decoder cores.