Aldec发布可重新配置的基于FPGA的加速器以用于高频交易应用

Henderson, Nev. – Dec 13, 2017 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, releases re-configurable FPGA-based accelerators dedicated for executing various types of High Frequency Trading (HFT) strategies demanding extraordinary low latency, throughput and computational power.

The newly released FPGA board complements the High-Performance Computing portfolio from which HFT applications can benefit due to dedicated features and specialization. Low latency which is the paramount requirement was achieved by using the newest generation Xilinx FPGA – Virtex UltraScale+ and connecting all critical interfaces like Ethernet, QSFP and PCI Express directly to the FPGA. The FPGA can be reconfigured on-the-fly without need of shutting down the entire system which greatly increases the flexibility of such configuration and facilitates quick reaction on dynamically changing trading conditions. The new FPGA accelerators are compatible with 1U and larger trading systems for time-sensitive trading strategies such as Market Making, Statistical Arbitrage and Algorithmic Trading.

“Due to the inherent re-programmability and massive parallel computing resources of FPGAs, we have seen more and more FPGA implementations of HFT trading systems over the last five years,” said Louie De Luna, Director of Marketing. “Our HFT solutions provide trading firms a development platform for FPGA designs, and as well as FPGA boards for execution of the trading strategies within deep sub-microsecond latency.”

The new board HES-HPC-HFT-XCVU9P is a re-configurable FPGA-based accelerator that contains 1x Virtex UltraScale+ XCVU9P FPGA (2.5M logic cells and 6840 DSP slices) with dual QSFP28 cages for high-bandwidth low-latency communications with market data and orders. The onboard QDR-II+ memories provide ultra-fast data rate transfers for applications requiring high throughput. The PCIe x16 half-length low-profile board enables maximum performance density in any enterprise rack server system for maximum performance density.

Customers looking for a complete FPGA development eco-system will benefit from cooperation with Aldec with its FPGA accelerator boards and RTL development/simulation tools such as Riviera-PRO – a high performance mixed-language (VHDL/Verilog/SystemVerilog/SystemC) simulator with Python testbench support for FPGAs, and integrate with IP partners providing IP-cores critical for implementing market data feed handlers and other blocks of the trading system.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Emulation/Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, High-Performance Computing and Military/Aerospace solutions. www.aldec.com