Kaiserslautern, Germany, Nov. 10, 2016 – Creonic GmbH today announced immediate availability of the new CCSDS AR4JA LDPC encoder and decoder IP core, following initial delivery to the first customer. The new core provides block length and code rate flexibility, complementing the field-proven CCSDS LDPC (8160, 7136) encoder and decoder IP core. It extends Creonic’s broadest product portfolio of LDPC IP cores on the market.
The CCSDS AR4JA LDPC codes are well known for their outstanding error correction performance when compared to other LDPC-based standards. Even though the CCSDS standard is meant for satellite communication in the first place, the unique properties of the IP core makes it the ideal fit for further applications with highest demands on error correction performance.
The forward error correction solution allows for throughputs of more than 200 Mbit/s. Payload block lengths of 1,024, 4,096 and 16,384 bits are supported. Each block length supports code rates 1/2, 2/3 and 3/4, resulting in nine LDPC codes overall. The cores are equipped with easy-to-use AXI4-Stream interfaces.
The new CCSDS IP core is available for ASIC and FPGA (Xilinx and Altera) technologies either as plain or encrypted source code. In addition, the core comes with HDL simulation models, self-checking testbench, bit-accurate Matlab, C or C++ simulation model and comprehensive documentation.
For more information, please visit the product page or contact us.
Creonic is an ISO 9001:2008 certified provider of ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The company offers the richest product portfolio in this field, covering standards like DVB-S2X, LTE-A, DVB-RCS2, DOCSIS 3.1, WiFi, WiGig, and UWB. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information please visit our website at www.creonic.com.