New Silicon IP
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IP Camera Front End
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Configurable CAN Bus Controller with Flexible Data-Rate
- Designed in accordance with ISO 11898‐1:2015 specification
- Supports CAN and CAN FD frames
- Supports up to 64 bytes of data frame
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Enhanced Multiprotocol Serial Communication Controller
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
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DCD's Universal Timers System
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Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
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SMBUS & PMBUS Master/Slave controller
- Master operation: Master transmitter, Master receiver
- Slave operation: Slave transmitter, Slave receiver
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TicoXS FIP UHD4K Encoder / Decoder IP-core with JPEG XS and Flawless Imaging Profile (FIP) - – The newest codec for AV over IP with 100% quality and zero latency !
- Extremely low footprint in FPGA or ASIC (low logic, low memory, low DDR)
- Compliant with JPEG XS High Profile & Flawless Imaging Profile (FIP)
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IrDA Controller
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
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I2C Master / Slave Controller with FIFO (AXI & AXI-Lite Bus)
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