The Memory Models for Wide I/O are ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have ...

This Cadence® Verification IP (VIP) provides support for the SPI protocol. The SPI VIP provides a complete bus functional model (BFM) and integrated automatic protocol checks. Designed for ...

SPI (Serial Peripheral Interface) Flash is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI Flash VIP can be used to verify Master or Slave device following ...

SPI (Serial Peripheral Interface) is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI VIP can be used to verify Master or Slave device following the SPI ...

SPI/BOSCH Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/BOSCH Verification IP is fully compliant with SPI Block Guide V04.01 ...

SPI/FRAM Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/SPANSION_FLASH Verification IP is fully compliant with SPI Block Guide ...

SPI/MACRONIX Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/MACRONIX Verification IP is fully compliant with SPI Block Guide ...

SPI/MOTOROLA Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/FLASH Verification IP is fully compliant with SPI Block Guide V04.01 ...

SPI/SERIAL FLASH Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/SERIAL FLASH Verification IP is fully compliant with SPI Block ...

SPI/SPANSION FLASH Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/SPANSION FLASH Verification IP is fully compliant with SPI ...

SPI/ST MEMS Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/ST MEMS Verification IP is fully compliant with SPI Block Guide V04.01 ...

Octal SPI is the serial synchronous communication protocol developed by Macronix(CMOS MXSMIOￂﾮ(SERIAL MULTI I/O) Flash memory).It includes an extensive test suite covering most of the possible ...

SPI Nand Flash Memory Model provides an smart way to verify the SPI Nand Flash protocols.It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog. ...

SPI/EEPROM Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/EEPROM Verification IP is fully compliant with SPI Block Guide V04.01 ...

SPI/RTC (Real time counter) Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV s SPI/RTC Verification IP is fully compliant with SPI Block ...

SPIStack is the serial synchronous communication protocol based Flash VIP, supporting all major SPIStack vendors. SPIStack Verification IP can be used to verify SPIStack Master or Slave in SOC. ...

Synopsys VC Verification IP (VIP) for SDIO is a comprehensive VIP solution enabling pre-silicon functional verification of SD (Secure Digital) IO/Memory/Combo designs.

SD-Xactor is a comprehensive VIP solution portfolio for SDIO 4.0 and UHS-II used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. SD-Xactor implements ...

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to ...

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to ...

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to ...

The Memory Models for Wide I/O 2 are ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have ...

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protocol. Incorporating the latest protocol updates, the Cadence® ...

xSPI in production since 2019 for many production designs. The Cadence® Memory Model Verification IP (VIP) for xSPI provides verification of xSPI (Expanded SPI) NOR flash devices using the ...

UST Global VIP for SPI provides a comprehensive set of verification, methodology and protocol features, thus enabling designers to achieve a faster convergence & closure of SPI designs. SPI ...

eSPI (Enhanced Serial Peripheral Interface) is the serial synchronous communication protocol. It includes an extensive test suite covering most of the possible scenarios. It performs all possible ...

xSPI (Expanded Serial Peripheral Interface) is the serial synchronous communication protocol developed by JEDEC eXpanded Serial Peripheral Interface (xSPI)for Non Volatile Memory Devices.It ...

QSPI (Quad Serial Peripheral Interface) VIP can be used to verify Master or Slave device following the QSPI basic protocol.It can work with Verilog HDL environment and works with all Verilog ...

SafeSPI is the serial synchronous communication protocol based Flash VIP, supporting all major SafeSPI vendors. SafeSPI Verification IP can be used to verify SafeSPI Master or Slave in SOC. ...

SATA Verification IP provides an smart way to verify the SATA bi-directional bus. The SmartDV s SATA Verification IP is fully compliant with revision 2.5/2.6/3.0/3.1/3.2/3.3/3.4 of the SATA ...

FRAM Memory Model provides an smart way to verify the FRAM component of a SOC or a ASIC. The SmartDV s FRAM memory model is fully compliant with standard FRAM Specification and provides the ...

HMC Memory Model provides an smart way to verify the HMC component of a SOC or a ASIC. The SmartDV s HMC memory model is fully compliant with standard HMC Specification and provides the following ...

The SmartDV s LVDS verifies the Radio Front end-Baseband digital parallel interface.LVDS VIP can be used to verify BBIC or RFIC and SPI Master or Slave following the LVDS basic protocol as defined ...

nvSRAM Memory Model provides an smart way to verify the nvSRAM component of a SOC or a ASIC. The SmartDV s nvSRAM memory model is fully compliant with standard nvSRAM Specification and provides ...

Parallel PCRAM Memory Model provides an smart way to verify the Parallel PCRAM component of a SOC or a ASIC. The SmartDV s Parallel PCRAM memory model is fully compliant with standard Parallel ...

RERAM Memory Model provides an smart way to verify the RERAM component of a SOC or a ASIC. The SmartDV s RERAM memory model is fully compliant with standard RERAM Specification and provides ...

SAS Verification IP provides an smart way to verify the SAS bi-directional bus. The SmartDV s SAS Verification IP is fully compliant with SAS 2.1, SAS 3.0, SAS 4.0,SAS 5.0, SAS Protocol Layer ...

SDIO 1.0, 2.0,3.0,4.20,5.0,5.10,6.0,6.10,7.0,7.10 and 8.0(Draft) VIP is an advanced solution in the market for the verification of SDIO 1.0/2.0/3.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft) ...

SERIAL PCRAM Memory Model provides an smart way to verify the SERIAL PCRAM component of a SOC or a ASIC. The SmartDV s SERIAL PCRAM memory model is fully compliant with standard SERIAL PCRAM ...

The Secure Digital Input Output (SDIO) interface is a card interface defined to connect a SD Host Controller with four different types of cards, namely SDIO card, SD memory card, SD Combo card ...