Rate ½ 802.16d Turbo Convolutional Code Encoder / Decoder

特色

• Encoder
• Fully compliant with 802.16d specification
• Available for Xilinx FPGA or ASIC implementation
• Compact design, uses 464 CLB slices, 2 Block
• Rams, and 1 Multiplier in Virtex II
• Clock speed reaches 102 MHz in Virtex II
• Fully synchronous one clock design
• Decoder
• Fully compliant with 802.16d specification. Supports all the data block lengths
• Available for Xilinx FPGA or ASIC implementation
• Compact design, uses 5851 CLB slices for four iterations, 32 Block Rams, and 1 multiplier in Virtex II, among the smallest on the market
• Clock speed reaches 82 MHz in Virtex II, supports data rate 30 to 40 Mbps depending on data block length
• No external noise power estimation
• 4 bit soft input for data and parity
• Power efficient interleaving operation
• Fully synchronous one clock design

可交付内容

• The rate 1/2 Turbo Convolutional Code for 802.16d is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification.

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