DP1.4 RX PHY_GlobalFoundries
The physical layer contains 4 data channels, an AUX channel and bias circuit.
The 4 data channels serve as the main link to receive video and audio stream with a data rate up to 8.1Gbps. Each data channel consists of termination, equalizer and CDR circuit.
The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status between a transmitter and a receiver device.
The bias circuit generates voltage and current reference.
The PHY logic receives the recovered parallel data and clocks signals of 4 data channels.
Innosilicon DP RX IP offers reliable implementation for DP or eDP interface, which can be integrated in the SOC used in multimedia device.
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eDP/DP IP
- eDP1.4/DP1.4 TX IP PHY
- eDP1.4/DP1.3 TX Link IP
- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP