Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output
Differential Clock Receiver - TSMC CLN3P
designed for digital logic processes and use robust design techniques to work in noisy SoC environments,
ranging from high speed communication to low power consumer applications.
The Receiver macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices at
core voltage only. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates
signal ESD structures and a power supply ESD structure.
查看 Differential Clock Receiver - TSMC CLN3P 详细介绍:
- 查看 Differential Clock Receiver - TSMC CLN3P 完整数据手册
- 联系 Differential Clock Receiver - TSMC CLN3P 供应商