This Cadence® Verification IP (VIP) provides support for the TileLink specification. It provides a highly capable compliance verification solution simulation, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for TileLink runs on all leading simulators. It supports user interfaces in SV-UVM, plain SV, and C. The VIP includes a bus functional model (BFM) with automatic protocol checkers, supports random stimuli, and collects functional coverage.
The TileLink protocol is a standard of the RISC-V Foundation® designed for RISC-V processors. TileLink is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices. TileLink is designed for use in a SoC to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complex devices, using a fast scalable interconnect providing both low-latency and high-throughput transfers.
The VIP for TileLink verifies the design under test (DUT) by providing active slave and master agents for generating and driving stimuli. It provides passive slave and master agents for checking the protocol and collecting coverage. The VIP agents are highly configurable to support any combination of protocol configurations and optional features. The VIP is architected to enhance design verification productivity, ensure high-quality designs, and deliver maximum performance.