IGALVDS04A FPD-link receiver converts the five LVDS (Low Voltage Differential Signaling) data streams back into parallel 18/24/30-bit of 1.1V CMOS data. The receiver’s outputs are falling edge strobe.
The IGALVDS04A requires only six line-termination resistors for the differential inputs. An active-low power down input can be used to inhibit the clock and shut off the LVDS receivers for lower power consumption.
- 2.5V/3.3V analog supply operation and 1.1V digital supply operation
- 60 to 100 MHz shift clock support (dual channel)
- Support spread spectrum clock tracking
- Falling-edge clock triggered outputs
- PLL lock detection output
- Support floating and terminated input fail-safe
- Support on die 100 Ω terminal enable/ disable
- Power-down capability