IGALVDV03A is a 5-channel LVDS Transmitter PHY IP, which is used mainly in Flat-panel Display. It enables larger, higher resolution displays and lowers component counts without increasing power consumption, bus interconnect or overall cost.
There is an internal de-skew Phase Locked Loop (PLL) to provide x7/x14 clock for LVDS TX functions.
The layout layer of IGALVDV03A is 1P11M (2Xa1Xd3Xe2Y2R).
- Operating junction temperature: -40℃~125℃
- Total 5 channels; 4 data pairs and 1 clock pair by default
- LVDS Input clock operation frequency: pll_ref_clk: 10MHz~110MHzclkin: 20MHz~220MHz
- LVDS Output data rate: 140Mbps~1540Mbps
- LVDS Input 7:1 parallel to serial ratio
- Output common mode voltage: 0.9V to 1.2V
- Adjustable Tx Clock/Data output driving: 1.5mA ~ 5mA
- Power down mode
- Tri-state and power off for individual Tx Data/Clock output