SiFive’s MCMR FEC IP core is a single solution to meet the requirements of different protocols like Interlaken, Flex Ethernet, and 802.3x to significantly improve bandwidth by enabling high speed SerDes integration. The FEC can easily achieve a BER (Bit Error Rate) of <10-15 with an input BER of >10-6, which is required by most electrical interface standards using high speed SerDes.
Built upon a flexible and robust architecture, SiFive’s MCMR FEC IP core is compatible with various SerDes supporting different widths. The MCMR FEC IP supports bandwidth up to 400G with the ability to connect 32 SerDes lanes.
- Supports up to 56Gbps SerDes
- Supports bandwidth up to 400G
- Support for KP4 RS (544,514) & KR4 RS (528,514)
- Supports Interlaken, Flex Ethernet & 802.3x protocols
- Supports configurable alignment marker
- PRBS test pattern generator and loopback test
- SiFive’s MCMR FEC IP core supports the Interlaken standard specification and the Ethernet standard specification.
- Designed and tested to be easily synthesizable into many ASIC technologies, the SiFive MCMR FEC IP core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor-specific proven SerDes allows for fast and seamless integration of the MCMR FEC IP core into the technology of choice.
- Synthesizable RTL
- Assertions for the user interface and config registers
- Sanity test simulation environment
- RX/TX BFMs
- SiFive-Silicon IP Specification
- Memory-Mapped Register Manual
- Design Verification Plan
- Packet Processing/NPU
- Traffic Management
- Switch Fabric
- Switch Fabric Interface
- Serial Memory
- FPGA etc.