You are here:
SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm)
M31 Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The Serdes IP supports data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-KR, CEI, XAUI, USXGMII, QSGMII, and SGMII. With the supports for both TX and RX equalization techniques, the Serdes IP is designed to meet the requirements for different channel conditions.
查看 SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm) 详细介绍:
- 查看 SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm) 完整数据手册
- 联系 SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm) 供应商
SerDes IP
- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- 125Mbps to 16Gbps Multi-protocol SerDes PMA
- 250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency